The present invention relates generally to integrated circuits (ICs), and more specifically, to a method and system for designing a test circuit in a System on Chip (SOC).
An SOC usually includes several logic elements. These logic elements include the design logic specific to the basic features of the SOC and the design logic specific to certain applications of the SOC. Designers have observed that the application specific design logic has a significant gate count in the SOC. As the gate count in the SOC design increases considerably, it requires a lot of testing strategy, effort and time to verify the SOC against manufacturing defects. There has been a continuous effort to reduce cost involved in the testing process of the SOC.
There exist some standard testing techniques such as inserting multiple scan chains in the SOC design. In these techniques, a set of test patterns are applied through the multiple scan chains to test the SOC design for faults. In most of these techniques, multiple scan chains are inserted inside the SOC logic. A set of scan patterns is applied and the patterns are propagated through the SOC design, producing output scan data that is checked to ensure that the output response is same as that of expected response.
These existing techniques do not take into account the application-specific aspect of the logic blocks of the SOC. In a typical SOC, each logic block of the application-specific logic is not necessarily for the use of the target user. In these techniques, the length of the longest scan chain, and the number of scan chains used during the testing of the SOC, remains the same, even if testing of some of the application-specific logic blocks is not required.